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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. adg528a/adg529a cmos latched 4-/8-channel analog multiplexers features 44 v supply maximum rating v ss to v dd analog signal range single-/dual-supply specifications wide supply ranges (10.8 v to 16.5 v) microprocessor compatible (100 ns wr pulse) extended plastic temperature range (?0 c to +85 c) low leakage (20 pa typ) low power dissipation (28 mw max) available in 18-lead dip/soic and 20-lead plcc packages superior alternative to: dg528 dg529 functional block diagrams general description the adg528a and adg529a are cmos monolithic analog multiplexers with eight channels and four dual channels, respec- tively. on-chip latches facilitate microprocessor interfacing. the adg528a switches one of eight inputs to a common output, depending on the state of three binary addresses and an enable input. the adg529a switches one of four differential inputs to a common differential output, depending on the state of two binary addresses and an enable input. both devices have ttl and 5 v cmos logic-compatible digital inputs. the adg528a and adg529a are designed on an enhanced lc 2 mos process, which gives an increased signal capability of v ss to v dd and enables operation over a wide range of supply voltages. the devices can comfortably operate anywhere in the 10.8 v to 16.5 v single- or dual-supply range. these multiplex- ers also feature high switching and low r on . product highlights 1. single-/dual-supply specifications with a wide tolerance. the devices are specified in the 10.8 v to 16.5 v range for both single- and dual-supplies. 2. easily interfaced the adg528a and adg529a can be easily interfaced with microprocessors. the wr signal latches the state of the address control lines and the enable line. the rs signal clears both the address and enable data in the latches result- ing in no output (all switches off). rs can be tied to the microprocessor reset pin. 3. extended signal range the enhanced lc 2 mos processing results in a high breakdown and an increased analog signal range of v ss to v dd . 4. break-before-make switching switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 5. low leakage leakage currents in the range of 20 pa make these multiplexers suitable for high precision circuits.
rev. b e2e adg528a/adg529aespecifications dual supply adg528a adg528a adg528a adg529a adg529a adg529a k version b version t version e40 c to e40 c to e55 c to parameter +25 c +85 c +25 c +85 c +25 c +125 c units comments analog switch analog signal range v ss v ss v ss v ss v ss v ss v min v dd v dd v dd v dd v dd v dd v max r on 280 280 280 typ e1 0 v v s +10 v, i ds = 1 ma; test circuit 1 450 600 450 600 450 600 max 300 400 300 400 max v dd = 15 v ( 10%), v ss = e15 v ( 10%) 300 400 max v dd = 15 v ( 5%), v ss = e15 v ( 5%) r on drift 0.6 0.6 0.6 %/ c typ e10 v v s +10 v, i ds = 1 ma r on match 5 5 5 % typ e10 v v s +10 v, i ds = 1 ma i s (off), off input leakage 0.02 0.02 0.02 na typ v1 = 10 v, v2 = 10 v; test circuit 2 150 150 15 0 na max i d (off), off input leakage 0.04 0.04 0.04 na typ v1 = 10 v, v2 = 10 v; test circuit 3 adg528a 1 100 1 100 1 100 na max adg529a 1 50 1 50 1 50 na max i d (on), on channel leakage 0.04 0.04 0.04 na typ v1 = 10 v, v2 = 10 v; test circuit 4 adg528a 1 100 1 100 1 100 na max adg529a 1 50 1 50 1 50 na max i diff , differential off output leakage (adg529a only) 25 25 25 na max v1 = 10 v, v2 = 10 v; test circuit 5 digital control v inh , input high voltage 2.4 2.4 2.4 v min v inl , input low voltage 0.8 0.8 0.8 v max i inl or i inh 111 a max v in = 0 to v dd c in digital input capacitance 8 8 8 pf max dynamic characteristics 1 t transition 200 200 200 ns typ v1 = 10 v, v2 = 10 v; test circuit 6 300 400 300 400 300 400 ns max t open 50 50 50 ns typ test circuit 7 25 10 25 10 25 10 ns min t on (en, wr ) 200 200 200 ns typ test circuits 8 and 9 300 400 300 400 300 400 ns max t off (en, rs ) 200 200 200 ns typ test circuits 8 and 10 300 400 300 400 300 400 ns max t w write pulse width 100 120 100 120 100 130 ns min see figure 1 t s address, enable setup time 100 100 100 ns min see figure 1 t h , address, enable hold time 10 10 10 ns min see figure 1 t rs reset pulse width 100 100 100 ns min see figure 2 off isolation 68 68 68 db typ v en = 0.8 v, r l = 1 k , c l = 15 pf, 50 50 50 db min v s = 7 v rms, f = 100 khz c s (off) 5 5 5 pf typ v en = 0.8 v c d (off) adg528a 22 22 22 pf typ v en = 0.8 v adg529a 11 11 11 pf typ q inj , charge injection 4 4 4 pc typ r s = 0 , v s = 0 v; test circuit 11 (v dd = +10.8 v to +16.5 v, v ss = e10.8 v to e16.5 v, unless otherwise noted.)
rev. b adg528a/adg529a e3e adg528a adg528a adg528a adg529a adg529a adg529a k version b version t version e40 c to e40 c to e55 c to parameter +25 c +85 c +25 c +85 c +25 c +125 cu nits comments power supply i dd 0.6 0.6 0.6 ma typ v in = v inl or v inh 1.5 1.5 1.5 ma max i ss 20 20 20 a typ v in = v inl or v inh 0.2 0.2 0.2 ma max power dissipation 10 10 10 mw typ 2.8 2.8 2.8 mw max note 1 sample tested at +25 c to ensure compliance. specifications subject to change without notice. single supply adg528a adg528a adg528a adg529a adg529a adg529a k version b version t version e40 c to e40 c to e55 c to parameter +25 c +85 c +25 c +85 c +25 c +125 cu nits comments analog switch analog signal range gnd gnd gnd gnd gnd gnd v min v dd v dd v dd v dd v dd v dd v max r on 500 500 500 typ gnd v s +10 v, i ds = 0.5 ma; test circuit 1 700 1000 700 1000 700 1000 max r on drift 0.6 0.6 0.6 %/ c typ gnd v s +10 v, i ds = 0.5 ma r on match 5 5 5 % typ gnd v s +10 v, i ds = 0.5 ma i s (off), off input leakage 0.02 0.02 0.02 na typ v1 = +10 v/gnd, v2 = gnd/+10 v; 15 01 50 1 50 na max test circuit 2 i d (off), off input leakage 0.04 0.04 0.04 na typ v1 = +10 v/gnd, v2 = gnd/+10 v; adg528a 1 100 1 100 1 100 na max test circuit 3 adg529a 1 50 1 50 1 50 na max i d (on), on channel leakage 0.04 0.04 0.04 na typ v1 = +10 v/gnd, v2 = gnd/+10 v; adg528a 1 100 1 100 1 100 na max test circuit 4 adg529a 1 50 1 50 1 50 na max i diff , differential off output leakage (adg529a only) 25 25 25 na max v1 = +10 v/gnd, v2 = gnd/+10 v; test circuit 5 digital control v inh , input high voltage 2.4 2.4 2.4 v min v inl , input low voltage 0.8 0.8 0.8 v max i inl or i inh 111 a max v in = 0 to v dd c in digital input capacitance 8 8 8 pf max dynamic characteristics 1 t transition 300 300 300 ns typ v1 = +10 v/gnd, v2 = gnd/+10 v; test circuit 6 450 600 450 600 450 600 ns max t open 50 50 50 ns typ test circuit 7 25 10 25 10 25 10 ns min t on (en, wr ) 250 250 250 ns typ test circuits 8 and 9 450 600 450 600 450 600 ns max t off (en, rs ) 250 250 250 ns typ test circuits 8 and 10 450 600 450 600 450 600 ns max t w write pulse width 100 120 100 120 100 130 ns min see figure 1 (v dd = +10.8 v to +16.5 v, v ss = gnd = 0 v, unless otherwise noted.)
rev. b e4e adg528a/adg529a adg528a adg528a adg528a adg529a adg529a adg529a k version b version t version e40 c to e40 c to e55 c to parameter +25 c +85 c +25 c +85 c +25 c +125 c units comments dynamic characteristics 1 (cont?d) t s address, enable setup time 100 100 100 ns min see figure 1 t h address, enable hold time 10 10 10 ns min see figure 1 t rs reset pulse width 100 100 100 ns min see figure 2 off isolation 68 68 68 db typ v en = 0.8 v, r l = 1 k , c l = 15 pf, 50 50 50 db min v s = 3.5 v rms, f = 100 khz c s (off) 5 5 5 pf typ v en = 0.8 v c d (off) adg528a 22 22 22 pf typ v en = 0.8 v adg529a 11 11 11 pf typ q inj , charge injection 4 4 4 pc typ r s = 0 , v s = 0 v; test circuit 11 power supply i dd 0.6 0.6 0.6 ma typ v in = v inl or v inh 1.5 1.5 1.5 ma max power dissipation 11 10 10 mw typ 25 25 25 mw max note 1 sample tested at +25 c to ensure compliance. specifications subject to change without notice.
rev. b adg528a/adg529a e5e ordering guide temperature package package model range description option 1 adg528akn e40 c to +85 c pdip n-18 adg528akp e40 c to +85 c plcc p-20a adg528akp-reel e40 c to +85 c plcc p-20a adg528abq e40 c to +85 c cerdip q-18 adg528atq e55 c to +125 c cerdip q-18 adg528abchips die adg528atchips die adg529akn e40 c to +85 c pdip n-18 adg529akp e40 c to +85 c plcc p-20a adg529akrw e40 c to +85 c soic rw-18 adg529akrw-reel e40 c to +85 c soic rw-18 ADG529AKRW-REEL7 e40 c to +85 c soic rw-18 adg529abq e40 c to +85 c cerdip q-18 adg529atq e55 c to +125 c cerdip q-18 adg529abchips die adg529atchips die notes 1 n = plastic dip; p = plastic leaded chip carrier (plcc); q = cerdip; rw = soic. absolute maximum ratings 1 (t a = +25 c, unless otherwise noted) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e25 v analog inputs 2 voltage at s, d . . . . . . . . . v ss e 2 v to v dd + 2 v or 20 ma, whichever occurs first continuous current, s or d . . . . . . . . . . . . . . . . . . . 20 ma pulsed current, s or d 1 ms duration, 10% duty cycle . . . . . . . . . . . . . . . 40 ma digital inputs 1 voltage at a, en, wr , rs . . . . . . v ss e 4 v to v dd + 4 v or 20 ma, whichever occurs first power dissipation (any package) up to +75 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mw derates above +75 c . . . . . . . . . . . . . . . . . . . . . . . 6 mw/ c operating temperature commercial (k version) . . . . . . . . . . . . . . . e40 c to +85 c industrial (b version) . . . . . . . . . . . . . . . . . e40 c to +85 c extended (t version) . . . . . . . . . . . . . . . . e55 c to +125 c storage temperature range . . . . . . . . . . . . . e65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 overvoltage at a, en, wr , rs , s or d will be clamped by diodes. current should be limited to the maximum rating above. pin configurations caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg528a/adg529a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device plcc dip/soic
rev. b e6e adg528a/adg529a truth tables a2 a1 a0 en wr rs swr r s adg528a a1 a0 en wr rs swr r s adg529a timing diagrams figure 1. figure 2. figure 1 shows the timing sequence for latching the switch address and enable inputs. the latches are level sensitive; there- fore, while wr is held low, the latches are transparent and the switches respond to the address and enable inputs. this input data is latched on the rising edge of wr . figure 2 shows the reset pulse width, t rs , and reset turn-off time, t off ( rs ). note: all digital input signals rise and fall times measured from 10% to 90% of 3 v. t r = t f = 20 ns.
rev. b t ypical performance characteristicseadg528a/adg529a e7e the multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 v. tpc 1. r on as a function of v d (v s ): dual supply voltage, t a = +25 c tpc 2. leakage current as a function of temperature (note: leakage currents reduce as the supply voltages reduce) tpc 3. r on as a function of v d (v s ): single supply voltage, t a = +25 c tpc 4. trigger levels vs. power supply voltage, dual or single supply, t a = +25 c tpc 5. t transition vs. supply voltage: dual and single supplies, t a = +25 c (note: for v dd and |v ss | < 10 v; v1 = v dd /v ss , v2 = v ss /v dd . see test circuit 6) tpc 6. i dd vs. supply voltage: dual or single supply, t a = +25 c
rev. b e8e adg528a/adg529a t est circuits test circuit 1. r on test circuit 2. i s (off) test circuit 3. i d (off) test circuit 4. i d (on) test circuit 5. i diff test circuit 6. switching time of multiplexer, t transition test circuit 7. break-before-make delay, t open
rev. b adg528a/adg529a e9e test circuit 8. enable delay, t on (en), t off (en) test circuit 9. write turn-on time, t on ( wr r rs
rev. b e10e adg528a/adg529a terminology r on ohmic resistance between terminals d and s r on match difference between the ron of any two channels r on drift change in ron versus temperature i s (off) source terminal leakage current when the switch is off. i d (off) drain terminal leakage current when the switch is off. i d (on) leakage current that flows from the closed switch into the body. v s (v d )a nalog voltage on terminal s or d c s (off) channel input capacitance for off condition c d (off) channel output capacitance for off condition c in digital input capacitance t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 10% points of the digital input and switch off condition t transition delay time between the 50% and 90% points of the digital inputs and switch on condition when switching from one address state to another. t open off time measured between 50% points of both switches when switching from one address state to another v inl maximum input voltage for logic 0 v inh minimum input voltage for logic 1 i inl (i inh ) input current of the digital input v dd most positive voltage supply v ss most negative voltage supply i dd positive supply current i ss negative supply current outline dimensions 18-lead plastic dual in-line package [pdip] (n-18) dimensions shown in inches and (millimeters) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.022 (0.558) 0.014 (0.356) 0.150 (3.81) 0.110 (2.79) 0.100 (2.54) bsc 0.060 (1.52) 0.045 (1.14) 18 1 9 10 0.885 (22.48) 0.845 (21.46) 0.295 (7.49) 0.275 (6.99) 0.015 (0.381) 0.008 (0.203) 0.325 (8.26) 0.300 (7.62) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095ad 0.180 (4.57) max 20-lead plastic leaded chip carrier [plcc] (p-20a) dimensions shown in inches and (millimeters) 0.020 (0.50) r bottom view (pins up) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) min 0.120 (3.04) 0.090 (2.29) 3 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.02) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.050 (1.27) bsc 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) r compliant to jedec standards mo-047aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design
rev. b adg528a/adg529a e11e outline dimensions 18-lead standard small outline package [soic] wide body (rw-18) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ab seating plane 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 18 10 9 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 11.75 (0.4626) 11.35 (0.4469) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) 18-lead ceramic dual in-line package [cerdip] (q-18) dimensions shown in inches and (millimeters) 18 19 10 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.960 (24.38) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 15 0 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design
rev. b c03337e0e10/04(b) e12e adg528a/adg529a revision history location page 10/04?data sheet changed from rev. a to rev. b deleted 20-lead lcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 soic added to dip pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

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